电子知识_MCP37231－200 200Msps 16位ADC模数转换方案

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MCP37231－200 200Msps 16位ADC模数转换方案

来源：互联网 | 作者:中华IC网整理 | 发表于：2014-12-09

Microchip MCP37231－200 200Msps 16位ADC模数转换方案,本文介绍了MCP37231/21-200主要特性,框图, ADC核框图以及MCP37X3X-200 16位200 MSPS ADC VTLA评估板ADM00505主要特性,框图,电路图,材料清单和PCB元件布局图.

Microchip公司的MCP37231/21-200是16位/14位200Msps ADC系列产品,每路内置了高阶数字抽取滤波器,增益,和失调调整,以及分数延迟恢复.器件具有谐波失真修正和DAC噪音消除,SNR大于74dBFS,SFDR大于90dBFS,200Msps的功耗仅为490mW,主要用在通信基础设施, 蜂窝基站,雷达,工业和消费类数据采集系统,扫描仪和手持仪器,超声以及声纳图像.本文介绍了MCP37231/21-200主要特性,框图, ADC核框图以及MCP37X3X-200 16位200 MSPS ADC VTLA评估板ADM00505主要特性,框图,电路图,材料清单和PCB元件布局图.

The MCP37231/21-200 is Microchip’s baseline 16-/14-bit 200 Msps pipelined ADC family, featuring built-in high-order digital decimation filters, gain and offset adjustment per channel, and fractional delay recovery.

The MCP37D31/21-200 device family features a digital down-conversion and CW beamforming capability, in addition to the features offered by the MCP37231/21-200.All devices feature harmonic distortion correction and DAC noise cancellation that enable high-performance specifications with SNR of greater than 74 dBFS, and SFDR of greater than 90 dBFS.

These A/D converters exhibit industry leading lowpower performance with only 490 mW operation while using the LVDS interface at 200 Msps. This superior low-power operation coupled with high dynamic performance makes these devices ideal for various high-performance, high-speed data acquisition systems including communications equipment, radar and portable instrumentation.

The output decimation filter option improves SNR performance up to 93.5 dBFS with the 512x decimation setting. The digital down-conversion option in conjunction with the decimation and quadrature output options offer great flexibility in digital communication system design, including cellular base-stations and narrow-band communications. Gain, phase and DC offset can be adjusted independently for each input channel, allowing for simplified implementation of CW beamforming and ultrasound Doppler imaging applications.

These devices can have up to eight differential input channels through an input MUX. The sampling rate is up to 200 Msps when a single channel is used, or 25 Msps per channel when all 8-input channels are used.

The differential full-scale analog input range is programmable up to 2.975 VP-P. The ADC output data can be coded in two’s complement or offset binary representation, with or without the data randomizer option. The output data is available as full rate CMOS or double data rate (DDR) LVDS. Additionally, a serialized LVDS option is also available for the 16-bit octal-channel mode.

The device is available in a Pb-free VTLA-124 and TFBGA-121 packages. The device operates over the commercial temperature range of -40°C to +85°C.

MCP37231/21-200主要特性:

• Sample Rates:
- 200 Msps for single-channel mode
- 200 Msps/Number of channel used
• SNR with fIN = 15 MHz and -1 dBFS:
- >74 dBFS for 200 Msps
• SFDR with fIN = 15 MHz and -1 dBFS:
- >90 dBFS at 200 Msps
• Power Dissipation with LVDS Digital I/O:
- 490 mW for 200 Msps
• Power Dissipation with CMOS Digital I/O:
- 436 mW for 200 Msps, Output Clock = 100 MHz
• Power Dissipation Excluding Digital I/O:
- 390 mW for 200 Msps
• Power Saving Modes:
- 80 mW during Standby
- 33 mW during Shutdown
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Input Range: up to 2.975 VP-P
• Input Channel Bandwidth: 500 MHz
• Channel-to-Channel Crosstalk: >95 dB in Multi-Channel mode (Input = 15 MHz, -1 dBFS)
• Output Data Format:
- Parallel CMOS, DDR LVDS
- Serialized DDR LVDS (16-bit, octal-channel mode)
• Optional Output Data Randomizer
• Digital Signal Post-Processing (DSPP) Options:
- Decimation Filters for improved SNR
- Fractional Delay Recovery (FDR) for timedelay corrections in multi-channel operations (dual/octal-channel modes)
- Phase, Offset and Gain adjust of individual channels
- Digital Down-Conversion (DDC) with I/Q or fS/8 output (MCP37D31/21-200)
- Continuous Wave Beamforming for octalchannel mode (MCP37D31/21-200)
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
• Serial Peripheral Interface (SPI)
• Package Options:
- VTLA-124 (9 mm x 9 mm x 0.9 mm)
- TFBGA-121 (8 mm x 8 mm x 1.08 mm)
• No external reference decoupling capacitor required for TFBGA Package
• Industrial Temperature Range: -40℃ to +85℃
MCP37231/21-200典型应用:
• Communication Instruments
• Cellular Base Stations
• Radar
• Ultrasound and Sonar Imaging
• Scanners and Low-Power Portable Instruments

• Industrial and Consumer Data Acquisition System

图1. MCP37231/21－200框图

图2. MCP37231/21-200 ADC核框图

MCP37X3X-200 16位200 MSPS ADC VTLA评估板ADM00505

The MCP37X3X-200 16-Bit 200 Msps ADC VTLA Evaluation Board (ADM00505) is intended to demonstrate the performance of the MCP37X2X-200 and MCP37X3X-200 device families. This evaluation board is used together with:

• MCP37XXX High-Speed Pipeline ADC Data Capture Card (ADM00506)
• Pipeline ADC Utility Software

This chapter provides an overview of the MCP37X3X-200 16-Bit 200 Msps ADC VTLA Evaluation Kit and covers the following topics:

• What is the MCP37X3X-200 16-Bit 200 Msps ADC VTLA Evaluation Board (ADM00505)?
• What is the MCP37XXX High-Speed Pipeline ADC Data Capture Card (ADM00506)?
• What is the Pipeline ADC Utility Software?
• MCP37X3X-200 16-Bit 200 Msps ADC VTLA Evaluation Kit Requirements

This evaluation board supports the following Microchip high-speed ADC device families:

• The MCP37X2X-200/MCP37X3X-200, which is Microchip Technology Inc.’s baseline 14-/16-bit 200 Msps pipelined analog-to-digital converter (ADC) device family, featuring a built-in high-order digital decimation filter, gain and offset adjustment per channel, and fractional delay recovery.

• The MCP37D2X-200/MCP37D3X-200 device family, which features digital down-conversion and CW beamforming capability, in addition to the features offered by the baseline device family.